1. Technical Field
The invention relates generally to semiconductor devices, and more specifically, to methods for isolating field effect transistors semiconductor devices.
2. Background Art
In the formation of large scale integrated circuits using field effect transistors (FET), isolation between devices is of critical importance. For example, in complementary semiconductor device (CMOS) technology all the transistors on the same die traditionally share a common substrate (body) voltage when not isolated. Thus, when the threshold voltage of one FET (e.g., used for logic or memory integrated circuits) is increased, the threshold voltages of all the FETs on the die will also increase. This increase of threshold voltages not only impedes the performance of the logic and memory integrated circuits, but also decreases the switching margin of the overall circuit.
Hence, several methods have been developed to isolate individual devices. One method consists of using independent wells in forming each FET. Although this method successfully isolates each device, extra space is required in constructing a circuit, which makes it difficult to increase the packing density of CMOS and could result in a rather expensive circuit design. Another solution for isolating devices consists of the process of creating a trench at the boundary between two wells of different polarities (i.e., between a p-well region and an n-well region) so that the depth of the trench is greater than the depth of the wells. Unfortunately, it is difficult and may be costly to form a deep trench in a semiconductor substrate, and if formed, may cause defects such as crystal defects in the substrate and/or wells.
One solution that addresses the aforementioned problems is the formation of a well-within-a-well, or double well structure. Examples of these types of wells are found in the following U.S. Patents, which are herein incorporated by reference: U.S. Pat. No. 4,907,058, "Complementary Semiconductor Device Having a Double Well", issued March 1990 to Sakai; U.S. Pat. No. 5,262,345, "Complimentary Bipolar/CMOS Fabrication Method", issued November 1993 to Nasser et al.; and U.S. Pat. No. 5,473,183, "Semiconductor Device of a First Conductivity Type which has a First Well of a Second Conductivity Type Formed Therein and a Second Well of the First Conductivity Type Formed in the First Well and a Pair of MOSFET Formed in the First and Second Wells", issued December 1995 to Yonemoto. As discussed in these patents, the outer well of the double well structure provides the isolation to the inner well, allowing for compactibility and reliability of the circuit.
Unfortunately, although the aforementioned patents discuss a double well structure, the process of making these structures as described requires extra masks and extra masking steps. Not only does an extra mask take extra time and expense, but an extra mask makes it difficult, if impossible to align the two wells without any excess space between the wells, ultimately decreasing the performance of the circuit.